ARM3 SUPPORT

Introduction and Overview

The ARM3Support module provides commands to control the use of the ARM3 processor's cache, where one is fitted to a machine. The module will immediately kill itself if you try to run it on a machine that only has an ARM2 processor fitted.

Summary of facilities

There is also a SWI to turn the cache on or off. A further SWI forces the cache to be flushed. Finally, there is also a set of SWIs that control how various areas of memory interact with the cache.

The default setup is such that all RISC OS programs should run unchanged with the ARM3's cache enabled. Consequently, you are unlikely to need to use the SWIs (beyond, possibly, turning the cache on or off).

Notes

A few poorly-written programs may not work correctly with ARM3 processors, because they make assumptions about processor timing or clock rates.

Finding out more

For more details of the ARM3 processor, see the Acorn RISC Machine family Data Manual. VLSI Technology Inc. (1990) Prentice-Hall, Englewood Cliffs, NJ, USA: ISBN 0-13-781618-9.

SWI Calls

Cache_Control (SWI &280)


Turns the cache on or off

On entry

R0 = EOR mask
R1 = AND mask

On exit

R0 = old state (0 => cacheing was disabled, 1 => cacheing was enabled)

Interrupts

Interrupts are disabled
Fast interrupts are enabled

Processor mode

Processor is in SVC mode

Re-entrancy

Not defined

Use

This call turns the cache on or off. Bit 0 of the ARM3's control register 2 is altered by being masked with R1 and then exclusive ORd with R0: ie new value = ((old value AND R1) XOR R0). Bit 1 of the control register is also set, forcing the memory controller to use the same translation table for both User and Supervisor Modes (as indeed the MEMC chip should). Other bits of the control register are set to zero.

Related SWIs

None

Related vectors

None

Cache_Cacheable (SWI &281)


Controls which areas of memory may be cached

On entry

R0 = EOR mask
R1 = AND mask

On exit

R0 = old value (bit n set => 2MBytes starting at n*2MBytes are cacheable)

Interrupts

Interrupts are disabled
Fast interrupts are enabled

Processor mode

Processor is in SVC mode

Re-entrancy

Not defined

Use

This call controls which areas of memory may be cached (ie are cacheable). The ARM3's control register 3 is altered by being masked with R1 and then exclusive ORd with R0: ie new value = ((old value AND R1) XOR R0). If bit n of the control register is set, the 2MBytes starting at n*2MBytes are cacheable.

The default value stored is &FC007FFF, so ROM, the RAM disc and logical non-screen RAM are cacheable, but I/O space, physical memory and logical screen memory are not.

(You may find a value of &FC007CFF - which disables cacheing the RAM disc - gives better performance.)

Related SWIs

Cache_Updateable (SWI &282), Cache_Disruptive (SWI &283)

Related vectors

None

Cache_Updateable (SWI &282)


Controls which areas of memory will be automatically updated in the cache

On entry

R0 = EOR mask
R1 = AND mask

On exit

R0 = old value (bit n set => 2MBytes starting at n*2MBytes are cacheable)

Interrupts

Interrupts are disabled
Fast interrupts are enabled

Processor mode

Processor is in SVC mode

Re-entrancy

Not defined

Use

This call controls which areas of memory will be automatically updated in the cache when the processor writes to that area (ie are updateable). The ARM3's control register 4 is altered by being masked with R1 and then exclusive ORd with R0: ie new value = ((old value AND R1) XOR R0). If bit n of the control register is set, the 2MBytes starting at n*2MBytes are updateable.

The default value stored is &00007FFF, so logical non-screen RAM is updateable, but ROM/CAM/DAG, I/O space, physical memory and logical screen memory are not.

Related SWIs

Cache_Cacheable (SWI &281), Cache_Disruptive (SWI &283)

Related vectors

None

Cache_Disruptive (SWI &283)


Controls which areas of memory cause automatic flushing of the cache on a write

On entry

R0 = EOR mask
R1 = AND mask

On exit

R0 = old value (bit n set => 2MBytes starting at n*2MBytes are disruptive)

Interrupts

Interrupts are disabled
Fast interrupts are enabled

Processor mode

Processor is in SVC mode

Re-entrancy

Not defined

Use

This call controls which areas of memory cause automatic flushing of the cache when the processor writes to that area (ie are disruptive). The ARM3's control register 5 is altered by being masked with R1 and then exclusive ORd with R0: ie new value = ((old value AND R1) XOR R0). If bit n of the control register is set, the 2MBytes starting at n*2MBytes are updateable.

The default value stored is &F0000000, so the CAM map is disruptive, but ROM/DAG, I/O space, physical memory and logical memory are not. This causes automatic flushing whenever MEMC's page mapping is altered, which allows programs written for the ARM2 (including RISC OS itself) to run unaltered, but at the expense of unnecessary flushing on page swaps.

Related SWIs

Cache_Cacheable (SWI &281), Cache_Updateable (SWI &282)

Related vectors

None

Cache_Flush (SWI &284)


Flushes the cache

On entry

-

On exit

-

Interrupts

Interrupts are disabled
Fast interrupts are enabled

Processor mode

Processor is in SVC mode

Re-entrancy

Not defined

Use

This call flushes the cache by writing to the ARM3's control register 1.

Related SWIs

None

Related vectors

None

*Cache

Turns the cache on or off, or gives the cache's current state

Syntax

*Cache [On|Off]

Parameters

On or Off

Use

*Cache turns the cache on or off. With no parameter, it gives the cache's current state.

Example

*Cache Off

Related commands

*Configure Cache

Related SWIs

Cache_Control (SWI &280)

Related vectors

None

*Configure Cache

Sets the configured cache state to be on or off

Syntax

*Configure Cache On|Off

Parameters

On or Off

Use

*Configure Cache sets the configured cache state to be on or off.

Example

*Configure Cache On

Related commands

*Cache

Related SWIs

Cache_Control (SWI &280)

Related vectors

None